As integrated circuits (ICs) become more advanced, feature sizes are reduced to achieve higher performance and to place more circuits on a single chip. The smaller feature sizes make the ICs more sensitive to damage from voltage levels that are used. To reduce the likelihood of such damage occurring, operating voltage levels are being reduced, e.g. to 2 volts or less. Reduction in operating voltage also requires a similar reduction in threshold voltage (V.sub.T) to keep noise margins and other operational factors in scale.
Unfortunately, as threshold voltages are reduced, the MOSFETS leak current at a higher rate than at the higher voltages when the MOSFETS are "off". This effect is caused by subthreshold current, which becomes more significant as threshold voltages are reduced.
Several different techniques have been used in the past to avoid the subthreshold leakage, most of which involve placing switches between the low V.sub.T MOS circuits and power supplies, to electrically isolate the MOS devices when they are off. A description of a prior art technique may be found in "Low Voltage Circuit Design Techniques for Battery-Operated and/or Giga-Scale DRAMs", by Tadato Yamagata et al, IEEE Journal of Solid-State Circuits, Vol. 30, No. Nov. 11, 1995, pp. 1183-1188.
A prior art circuit is shown in FIG. 1, wherein a low threshold (V.sub.T) MOS circuit 1 is connected via switches 3 and 5 to power supply rails of VDD and ground (VSS). Signals applied to the switches 3 and 5 cause them to close for normal operation and open for low power standby operation. Assuming the switches to be perfect, leakage current through circuit 1 would be stopped when the switches are open.
However, the switches 3 and 5 are not perfect, as they are realized by MOSFETS 7 and 9 as shown in FIG. 2. The MOSFETS 7 and 9 have their source-drain circuits in series with circuit 1 to voltage rails VDD and ground, respectively. MOSFETS 7 and 9 are typically realized as PMOS (p-channel MOS) and NMOS (n-channel MOS) high V.sub.T FETs respectively, in order to have low subthreshold leakage currents, and therefore to function as an effective off switch to stop subthreshold current leakage through circuits 1. Low V.sub.T devices are used in circuits 1 in order to provide acceptable propagation delay during normal operation.
To operate the switches, a signal STBY is applied to FET 7, which when pulled to VSS causes FET 7 to operate for normal operation of circuit 1, and when pulled to VDD causes FET 7 to become nonconductive, during a low power standby mode of circuit 1.
A signal /STBY is applied to FET 9, which when pulled high to VDD causes FET 9 to operate for normal operation of circuit 1, and when pulled low to VSS causes FET 9 to become nonconductive, during the low power standby mode of circuit 1.
Thus the high V.sub.T devices controlled by the STBY and /STBY signals, having lower subthreshold leakage currents than the devices used in circuits 1, limit subthreshold leakage during standby. The FETs 7 and 9 controlled by the STBY and /STBY signals may be local to a small or to a large group or to groups of logic circuits, to suit the design.
However, the circuit shown in FIG. 2 requires more processing steps than is desirable. To fabricate both high and low V.sub.T NMOS and PMOS devices in the same integrated circuit, extra masks are required to isolate the high V.sub.T devices from the low V.sub.T devices and requires additional fabrication steps. This can reduce yield and increase manufacturing costs.
FIG. 3 illustrates a variation of the above circuit, in which only a single switch is used. The circuit 1 in this case is shown as a complementary symmetry MOS (CMOS) inverter 11 formed of a PMOS and an NMOS FET having their source drain circuits connected in series, one end thereof being connected to VDD. The gates of the CMOS FETs are connected together to an input IN and the junctions of their source and drain circuits forms the output OUT.
An NMOS FET 13, used as a switch, is connected between the other end of the source drain circuit of the inverter 11 and ground. A high valued resistor 15 is connected across the source and drain of FET 13.
In this example, OUT is known to be at high logic level during the time that the inverter 11 is in its standby state, and therefore no power switch is required in its pull-up path. Control signal /STBY is pulled low to disable FET 13 during the standby time. The subthreshold leakage current I.sub.ST through the off NMOS FET of inverter 11 is in this case shunted through the resistor 15 to ground. This current induces a voltage drop across the resistor which increases the voltage V.sub.S at the source of the NMOS FET of the inverter 11. The increase in V.sub.S decreases the gate to source voltage of the NMOS FET of inverter 11 and therefore acts to turn that FET off harder, and effectively reduces the subthreshold leakage current I.sub.ST through that FET.
While the circuit of FIG. 3 has the advantage that no nodes float during the standby time, since only the "off" pull up or pull down path is effected, a high V.sub.T device is still required for FET 13, with the attendant increased fabrication complexity, cost and yield risk described with reference to the structure of FIG. 2. In addition, the resistor is a large device in an integrated circuit, which consumes precious silicon area.